Abstract - Modular exponentiation is the basic operation in cryptography algorithm RSA. This’s a complicated algorithm, consuming resource and time to implement (especially with large number). Hardware implementation of modular exponentiation on the FPGA would increase speed, reduce computation time that is required by the practice. The heart of modular operand is modular multiplication of large number. In this paper we presented introduction, the analysis, choosing modular exponentiation algorithm and modular multiplication Montgomery based on several public researchs on the world. Modular exponentiation operation is implemented with hardware language HDL Verilog with the modulus is chosen as 2048 bit, chip FPGA XC7z045. Implementation results of modular exponentiation with two different designs of IPcore Montgomery is briefly presented in Table 1 and Table 2.
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TÀI LIỆU THAM KHẢO
[1]. A. Menezes, P. van Oorschot and S. Vanstone.. "Handbook of Applied Cryptography", CRC Press, 1996.
[2]. Ranjeet Behera, Pradhan Abhisek, “FPGA Implementation of RSA algorithm and to develop a crypto based security system”, National Institute of Technology, Rourkela, 2012-2013. [3]. D. J. ANITHA, G. SUJATHA, P. JAYARAMI REDDY, “High Speed Low Cost New Semi Carry Save Adder Montgomery Modular Multiplier”, International Journal of Scientific Engineering and Technology Research, 2016. [4]. Mclvor, Ciaran, Maire McLoone, and John V. McCanny. "Fast Montgomery modular multiplication and RSA cryptographic processor architectures.", Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on. Vol. 1. IEEE, 2003. [5]. FIPS PUB 186-4. “Digital Signature Standard (DSS”). July, 2013. |
Thông tin trích dẫn : Trần Văn Thắng, Hoàng Văn Thức, " Về một giải pháp cứng hóa phép tính lũy thừa modulo ", Nghiên cứu Khoa học và Công nghệ trong lĩnh vực An toàn thông tin, Tạp chí An toàn thông tin, Vol.08, pp 45-51, No.02, 2018.
